FPGA implementation of hardware accelerated RTOS based on real-time event handling

Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective this paper is to present results obtained following implementation operating systems (RTOS) functions hardware. Based on resource multiplication concept, actual researches has been focused synthesizing field-programmable gate array (FPGA) implementing innovative solutions improve RTOS performance. are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency plus performance obtained. experimental results, FPGA requirements for processor different configurations, comparisons other similar presented order verify theoretical aspects proposed through paper.